• DocumentCode
    1385880
  • Title

    Monte Carlo simulator for the design optimization of low-noise HEMTs

  • Author

    Mateos, Javier ; González, Tomás ; Pardo, Daniel ; Hoël, Virginie ; Cappy, Alain

  • Author_Institution
    Dept. de Fisica Aplicada, Salamanca Univ., Spain
  • Volume
    47
  • Issue
    10
  • fYear
    2000
  • fDate
    10/1/2000 12:00:00 AM
  • Firstpage
    1950
  • Lastpage
    1956
  • Abstract
    A complete analysis of low-noise 0.1 μm gate AlInAs-GaInAs HEMT´s has been performed by using a semiclassical Monte Carlo simulation. The validity of the model has been checked through the comparison of the simulated results with static, dynamic and noise experimental measurements of real HEMTs. In order to reproduce the experimental results, we have included in the model some important real effects such as degeneracy, surface charges, T-shape of the gate, presence of dielectrics and contact resistances. Moreover, the extrinsic parameters of the devices have been added to the usual intrinsic small-signal equivalent circuit, thus allowing the calculation of the real noise of the HEMTs (characterized using the extrinsic minimum noise figure). In this way, we make possible not only the comparison with the experimental noise results, but also the analysis of the influence of the parasitic elements, the device width or the number of gate fingers on the noise of the HEMTs. The reliability of the simulator allows us to realize “computer experiments” which will make faster and cheaper the optimization process of the device design
  • Keywords
    III-V semiconductors; Monte Carlo methods; aluminium compounds; contact resistance; equivalent circuits; gallium arsenide; high electron mobility transistors; indium compounds; semiconductor device models; semiconductor device noise; simulation; 0.1 micron; AlInAs-GaInAs; HEMT noise calculation; Monte Carlo simulator; T-shaped gate; contact resistances; degeneracy; design optimization; device width; dielectrics; extrinsic device parameters; extrinsic minimum noise figure; gate fingers number; intrinsic small-signal equivalent circuit; low-noise HEMTs; parasitic elements; surface charges; Circuit noise; Design optimization; Dielectric measurements; Electrical resistance measurement; HEMTs; MODFETs; Monte Carlo methods; Noise figure; Noise measurement; Performance analysis;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.870579
  • Filename
    870579