• DocumentCode
    1385964
  • Title

    BF2 and boron double-implanted source/drain junctions for sub-0.25-μm CMOS technology

  • Author

    Fu-Cheng Wang ; Bulucea, C.

  • Author_Institution
    Nat. Semicond. Corp., Santa Clara, CA, USA
  • Volume
    21
  • Issue
    10
  • fYear
    2000
  • Firstpage
    476
  • Lastpage
    478
  • Abstract
    A double implant source/drain junction formation process using BF2 and boron is proposed for PMOSFET in sum-0.25-μm CMOS technology. Compared to the more conventional, single implant processes using BF2, the double implant process with downscaled BF2 implant energy offers the advantages of lower junction capacitance, less boron penetration, thinner gate oxide, and wider process window, as experimentally demonstrated.
  • Keywords
    CMOS integrated circuits; MOSFET; boron compounds; capacitance; elemental semiconductors; ion implantation; silicon; 0.18 micron; CMOS technology; PMOSFET; Si:B; Si:BF/sub 2/; boron penetration; double-implanted source/drain junctions; downscaled implant energy; gate oxide thickness; junction capacitance; process window width; Boron; CMOS process; CMOS technology; Capacitance; Degradation; Implants; MOSFET circuits; Manufacturing processes; Semiconductor diodes;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.870606
  • Filename
    870606
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1385964