A new poly-Si thin-film transistor with poly-Si/a-Si double active layer

Author

Park, Kee-Chan ; Choi, Kwon-Young ; Yoo, Juhn-Suk ; Han, Min-Koo

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

21

Issue

10

fYear

2000

Firstpage

488

Lastpage

490

Abstract

A new poly-Si TFT employing a rather thick poly-Si (400 /spl Aring/)/a-Si(4000 /spl Aring/) double active layer is proposed and fabricated in order to improve the stability of poly-Si TFT without sacrificing the on/off current ratio. Due to the thick double layer the on-state drain current of the proposed TFT flows through a broad current path near the drain junction so that the current density in the drain depletion region where large electric field is applied is considerably reduced. Consequently, additional trap state generation attributed to large current flow and large electric field in poly-Si channel decreases and the electrical stability of the proposed device has been considerably improved.

Keywords

amorphous semiconductors; current density; electron traps; elemental semiconductors; silicon; thin film transistors; 400 angstrom; 4000 angstrom; Si-Si; current density; current flow; double active layer; drain depletion region; drain junction; electric field; electrical stability; on-state drain current; on/off current ratio; polysilicon thin-film transistor; trap state generation; Charge carrier density; Computer simulation; Current density; Degradation; Electric variables; Passivation; Silicon; Stability; Stress; Thin film transistors;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.870610

Filename

870610