A multiple fault-tolerant processor network architecture for pipeline computing

Author

Tyszer, Jerzy

Author_Institution

Comput. Center, Tech. Univ., Poznan, Poland

Volume

37

Issue

11

fYear

1988

fDate

11/1/1988 12:00:00 AM

Firstpage

1414

Lastpage

1418

Abstract

Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m-1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m -2) faults. The configuration algorithm is fully distributed, and is performed on the basis of test results obtained from nonfaulty processors only. A simple fault identification procedure is developed using the above routing algorithm

Keywords

fault location; fault tolerant computing; multiprocessor interconnection networks; pipeline processing; configuration algorithm; distributed architecture; fault diagnosis; fault identification procedure; fault-tolerant multiprocessor networks; graph connectivity; linear array interconnections; multiple fault-tolerant processor network architecture; nonfaulty processors; pipeline computing; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Computer architecture; Computer networks; Fault tolerance; Pipelines; Polynomials; Testing;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.8707

Filename

8707