DocumentCode :
1386418
Title :
A BiCMOS PLL-based data separator circuit with high stability and accuracy
Author :
Miyazawa, Shyoichi ; Horita, Ryutaro ; Hase, Kenichi ; Kato, Kazuo ; Kojima, Shinichi
Author_Institution :
Hitachi Ltd., Yokohama, Japan
Volume :
26
Issue :
2
fYear :
1991
fDate :
2/1/1991 12:00:00 AM
Firstpage :
116
Lastpage :
121
Abstract :
A data separator that can work in Winchester disk drives at a read/write speed of up to 30 Mb/s is described. To realize high stability and accuracy in reproducing data in high-speed transfers, a digital synchronization field detector and an analog dual-mode phase-locked loop (PLL) that has a phase detector which has constant gain in the data field, independent of pattern, are used. The dual-mode analog PLL has a wide decode margin, locks up quickly, and operates stably without being affected by the frequency deviation of data. The digital sync field detector is adjustment-free and detects sync fields very accurately. The IC incorporates a RLL 2-7 code encoder/decoder and a write compensator. Use of the 2-μm BiCMOS process keeps the total power consumption as low as 400 mW even at the high transfer rate of 30 Mb/s
Keywords :
BIMOS integrated circuits; decoding; encoding; magnetic disc storage; phase-locked loops; synchronisation; 2 micron; 30 Mbit/s; 400 mW; BiCMOS; IC; PLL-based data separator circuit; RLL 2-7 code; Winchester disk drives; constant gain; digital synchronization field detector; dual-mode analog PLL; encoder/decoder; high stability; high-speed transfers; phase detector; phase-locked loop; power consumption; read/write speed; run length limited code; write compensator; BiCMOS integrated circuits; Circuit stability; Decoding; Detectors; Disk drives; Frequency synchronization; Particle separators; Phase detection; Phase locked loops; Winches;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.68125
Filename :
68125
Link To Document :
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