DocumentCode
1386507
Title
A unified approach to topology generation and optimal sizing of floorplans
Author
Dasgupta, Partha S. ; Sur-Kolay, Susmita ; Bhattacharya, Bhargab B.
Author_Institution
MIS Group, Indian Inst. of Manage., Calcutta, India
Volume
17
Issue
2
fYear
1998
fDate
2/1/1998 12:00:00 AM
Firstpage
126
Lastpage
135
Abstract
Existing algorithms for floorplan topology generation by rectangular dualization usually do not consider sizing issues. In this paper, given a rectangularly dualizable adjacency graph and a set of aspect ratios of the modules, a topology which is likely to yield an optimally sized floorplan, is produced first in a top-down fashion by an AI-based search technique with novel heuristic estimates based on size parameters. It is shown that for any rectangular graph, there exists a feasible topology using only either straight or Z-cutlines recursively within a bounding rectangle. The significance of this result is four-fold: (1) considerable acceleration of the heuristic search, (2) topology generation with minimal number of nonslice cores, (3) guaranteed safe routing order without addition of pseudo modules, and (4) design of an efficient bottom-up heuristic for optimal sizing. Experimental results show that this integrated method elegantly solves floorplan optimization problem for general including inherently nonslicible adjacency graphs
Keywords
VLSI; circuit layout CAD; circuit optimisation; graph theory; integrated circuit layout; network routing; network topology; search problems; AI-based search technique; VLSI layout design; aspect ratios; bottom-up heuristic; floorplan optimization problem; floorplan topology generation; heuristic search; optimal sizing; rectangular graph; rectangularly dualizable adjacency graph; top-down fashion; Acceleration; Dynamic programming; Heuristic algorithms; Optimization methods; Polynomials; Routing; Simulated annealing; Topology; Very large scale integration; Yield estimation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.681262
Filename
681262
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