Title :
Implementation of the FFT butterfly with redundant arithmetic
Author :
Bruguera, J.D. ; Lang, T.
Author_Institution :
Dept. of Electron., Santiago de Compostela Univ., Spain
fDate :
10/1/1996 12:00:00 AM
Abstract :
We present an architecture for the implementation of the radix-4 FFT butterfly with redundant arithmetic, based on the utilization of carry-save adders and a signed-digit representation of the multipliers in the multiplications. As the carry propagation is eliminated, a high throughput is maintained with a reduced hardware cost when compared to other architectures based on carry-propagate additions
Keywords :
adders; carry logic; fast Fourier transforms; integrated logic circuits; logic circuits; mathematics computing; multiplying circuits; pipeline arithmetic; redundant number systems; carry-save adders; high throughput; multipliers; radix-4 FFT butterfly; redundant arithmetic; signed-digit representation; Adders; Computer architecture; Costs; Fixed-point arithmetic; Hardware; Integrated circuit technology; Propagation delay; Throughput; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
