Title :
A low-jitter mixed-mode DLL for high-speed DRAM applications
Author :
Kim, Jae Joon ; Lee, Sang-Bo ; Jung, Tae-Sung ; Kim, Chang-Hyun ; Cho, Soo-In ; Kim, Beomsup
Author_Institution :
Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Abstract :
This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-/spl mu/m triple-metal CMOS process and occupies a die area of 0.45 mm/sup 2/. Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply.
Keywords :
CMOS memory circuits; DRAM chips; clocks; delay lock loops; high-speed integrated circuits; jitter; mixed analogue-digital integrated circuits; 0.6 micron; 200 MHz; 3.3 V; 33 mW; 6.38 ps; I/O peripherals; clock deskewing method; deskewing circuits; die area; high-speed DRAM applications; jitter; locking speed; mixed-mode DLL; power consumption; resolution problem; triple-metal CMOS process; Circuits; Clocks; Delay lines; Energy consumption; Jitter; Monitoring; Phase locked loops; Random access memory; SDRAM; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
