Title :
Fast-switching frequency synthesizer with a discriminator-aided phase detector
Author :
Yang, Ching-Yuan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-/spl mu/m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.
Keywords :
CMOS analogue integrated circuits; discriminators; frequency synthesizers; phase detectors; phase locked loops; 0.35 micron; 120 mW; 3.3 V; CMOS process; PLL pull-in time; discriminator-aided phase detector; fast-switching frequency synthesizer; noise bandwidth; output phase noise; power consumption; supply voltage; switching speed; Bandwidth; CMOS process; Detectors; Energy consumption; Frequency synthesizers; Noise reduction; Phase detection; Phase locked loops; Phase noise; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
