Title :
Analog implementation of the FDTS/DF detection algorithm for magnetic recording
Author :
Jaworski, Ronald V. ; Harjani, Ramesh
Author_Institution :
MicroSystems Eng., Lakev Oswego, OR, USA
fDate :
9/1/1996 12:00:00 AM
Abstract :
An analog implementation of the fixed delay tree search algorithm for magnetic recording detection is presented. The circuit is designed using a 1.2 μm BICMOS process with NPN devices with an ft of 12 GHz, and provides a reference for the feasibility of an analog implementation. Composite simulation results of all the system blocks suggest operating speeds in excess of 100 MSamples/s with a total power consumption of less than 1 W
Keywords :
BiCMOS analogue integrated circuits; decision feedback equalisers; delays; integrated circuit design; magnetic disc storage; sample and hold circuits; signal detection; tree searching; 1.2 micron; 12 GHz; BICMOS process; FDTS/DF detection algorithm; NPN devices; analog implementation; composite simulation; decision feedback; fixed delay tree search algorithm; magnetic recording; operating speeds; recording detection; total power consumption; Analog circuits; Analog computers; BiCMOS integrated circuits; Circuit synthesis; Decision feedback equalizers; Detection algorithms; Energy consumption; Magnetic recording; Maximum likelihood detection; Voltage;
Journal_Title :
Magnetics, IEEE Transactions on
