A new digital PLL for the Class I partial response channel

Author

Fukuda, Shinichi

Author_Institution

Adv. Dev. Lab., Sony Corp., Tokyo, Japan

Volume

32

Issue

5

fYear

1996

fDate

9/1/1996 12:00:00 AM

Firstpage

3974

Lastpage

3976

Abstract

A digital PLL (DPLL) for using the class I partial response (PR1) channel was developed as part of a PR1-channel decoder LSI for a digital data storage III system. As a channel clock generator of this DPLL, a ring oscillator whose period can be controlled by changing its inverter number was employed. An analog-to-digital converter for sampling the readback signal was placed in the main loop of the DPLL and was driven by the reconstructed channel clock, so no master clock is needed. This DPLL can generate a channel clock of 50 MHz

Keywords

CMOS digital integrated circuits; Viterbi detection; digital magnetic recording; digital phase locked loops; large scale integration; maximum likelihood detection; 50 MHz; CMOS; Class I partial response channel; LSI; PR1-channel decoder; Viterbi detection; analog-to-digital converter; channel clock generator; digital PLL; digital data storage; maximum likelihood detection; readback signal; reconstructed channel clock; Analog-digital conversion; Clocks; Decoding; Inverters; Large scale integration; Memory; Partial response channels; Phase locked loops; Ring oscillators; Sampling methods;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/20.539235

Filename

539235