On functional testing of array processors

Author

Sciuto, Donatella ; Lombardi, Fabrizio

Author_Institution

Dept. of Electr. & Comput. Eng., Colorado Univ.,. Boulder, CO, USA

Volume

37

Issue

11

fYear

1988

fDate

11/1/1988 12:00:00 AM

Firstpage

1480

Lastpage

1484

Abstract

This correspondence presents a new testing method for single instruction multiple data (SIMD) VLSI arrays. A new fault model is presented. Faults are defined at the functional level. A systematic test generation procedure is derived. Testing is performed by sequences of instructions. Two criteria are used. The first criterion establishes the external observability and controllability of the instructions. The second criterion uses instruction cardinality as a metric of instruction complexity. An example of the application of the proposed technique to an existing parallel scheme is described

Keywords

computer testing; controllability; observability; parallel algorithms; parallel architectures; SIMD VLSI arrays; array processors; controllability; fault model; functional testing; instruction cardinality; instruction complexity; observability; systematic test generation procedure; Computer science; Controllability; Distributed algorithms; Electrons; Fault diagnosis; Fault tolerance; Fault tolerant systems; Observability; System testing; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.8724

Filename

8724