A minimalist approach to VHDL logic modeling

The VHDL Design Exchange Group (VDEG), which consists of VHDL (VHSIC hardware description language) suppliers and users, was formed to promote the identical operation of VHDL models on different tools. One task of VDEG, which is still ongoing, is to develop a consensus logic model and a method for its use. VDEG and the VDEG´s work on this task as of September 1989 are described. The definition of portability used by VDEG and the minimalist approach toward a standard multivalue logic type for modeling favored by the group are examined. The use of the model is discussed. VDEG is developing a library of packages to aid in the construction of portable models; the package containing definitions of types of operations is described in some detail. Two mappings are presented to illustrate the assertion that the portable logic model is easy to map to the logic models in existing tools. Future work is outlined.<>