Title :
Circuit performance of CMOS technologies with silicon dioxide and reoxidized nitrided oxide gate dielectrics
Author :
Lee, Shiuh-Wuu ; Chan, Tung-Yi ; Wu, Albert T.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fDate :
7/1/1990 12:00:00 AM
Abstract :
The circuit performance of CMOS technologies with silicon dioxide (SiO/sub 2/) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V/sub GS/>
Keywords :
CMOS integrated circuits; dielectric thin films; integrated circuit technology; logic gates; 0 to 5 V; 100 to 300 K; CMOS inverter; CMOS technologies; RONO gate dielectrics; SiO/sub 2/ gate dielectric; SiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric; circuit performance; digital circuit operation; electron mobility; hole mobility; range of gate biases; reoxidized nitrided oxide gate dielectrics; temperatures ranging; CMOS digital integrated circuits; CMOS technology; Circuit optimization; Circuit simulation; Dielectrics; Digital circuits; Electron mobility; Inverters; Silicon compounds; Temperature distribution;
Journal_Title :
Electron Device Letters, IEEE
