Time memory cell VLSI for the PHENIX drift chamber

Author

Arai, Y. ; Ikeno, M. ; Sagara, M. ; Emura, T.

Author_Institution

Inst. of Particle & Nucl. Studies, KEK Nat. High Energy Accel. Res. Organ., Ibaraki, Japan

Volume

45

Issue

3

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

735

Lastpage

739

Abstract

A high-precision time-to-digital-converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and one level of trigger buffering required in very high rate experiments. In addition to a fixed data size readout, the chip also supports a zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 μsec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 μm CMOS gate-array technology

Keywords

CMOS memory circuits; VLSI; analogue-digital conversion; buffer circuits; drift chambers; nuclear electronics; trigger circuits; 37.6 MHz; CMOS gate-array technology; PHENIX drift chamber; RHIC bunch clock; TDC; TMC-PHX1; asymmetric ring oscillator; data buffering; high-precision time-to-digital-converter; readout FIFO; time memory cell VLSI; trigger buffering; very high rate experiments; zero-suppression mode readout; CMOS memory circuits; CMOS technology; Clocks; Computer buffers; Delay; Electronics packaging; Frequency; Phase locked loops; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.682626

Filename

682626