A high-speed and high-precision Winner-Select-Output (WSO) ASIC

Author

Yu, Haiming ; Miyaoka, Robert S. ; Lewellen, Tom K.

Author_Institution

Med. Center, Washington Univ., Seattle, WA, USA

Volume

45

Issue

3

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

772

Lastpage

776

Abstract

The design and performance characteristics of a 16-channel Winner-Select-Output (WSO) ASIC are presented. The WSO ASIC does a fast comparison of 16 analog input voltages, outputs the maximum signal, the “second” maximum (partner) signal, and their addresses. The WSO ASIC chip is a key component of an analog electronics system being developed for a depth of interaction (DOI) PET detector module. The basic cell of the WSO ASIC is a “winner take all” (WTA) circuit. The precision of the WSO ASIC is enhanced by using a cascade structure WTA cell. The chip requires a single +5 V supply and consumes 35 mW of power. The WSO ASIC is sensitive to voltage differences as small as 10 mV. The propagation delay of the chip is less than 30 nsec for voltage differences of >50 mW (typical for proposed application)

Keywords

application specific integrated circuits; detector circuits; nuclear electronics; 16-channel WSO ASIC; DOI PET detector module; WSO ASIC; WTA circuit; analog electronics system; analog input voltages; cascade structure WTA cell; depth of interaction PET detector module; high-speed high-precision Winner-Select-Output ASIC; maximum signal; performance characteristics; propagation delay; second maximum partner signal; voltage differences; winner take all circuit; Application specific integrated circuits; CMOS technology; Decoding; Detectors; Face detection; Mirrors; Photonic crystals; Positron emission tomography; Propagation delay; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.682634

Filename

682634