• DocumentCode
    1390631
  • Title

    Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

  • Author

    Ericson, M.N. ; Allen, M.D. ; Boissevain, J. ; Britton, C.L., Jr. ; Emery, M.S. ; Hah, S.F. ; Kapustinsky, J.S. ; Lind, R.E. ; Musrock, M.S. ; Simon-Gillo, J. ; Smith, D.E. ; Sullivan, J.P. ; Van Hecke, H. ; Young, G.R. ; Smith, M.C.

  • Author_Institution
    Oak Ridge Nat. Lab., TN, USA
  • Volume
    45
  • Issue
    3
  • fYear
    1998
  • fDate
    6/1/1998 12:00:00 AM
  • Firstpage
    833
  • Lastpage
    837
  • Abstract
    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented
  • Keywords
    data acquisition; field programmable gate arrays; high energy physics instrumentation computing; multichip modules; nuclear electronics; position sensitive particle detectors; silicon radiation detectors; FPGA-based circuit; PHENIX Multiplicity Vertex Detector; communication rates; control electronics; data format; error handling; formatting; front-end module readout; heap manager; interfaces; mode control; serial architecture; timing; Circuits; Communication system control; Detectors; Error correction; Field programmable gate arrays; Functional programming; Laboratories; Silicon; Strips; Timing;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.682646
  • Filename
    682646