Title :
FAIR: a new fast trigger and readout bus system
Author :
Ordine, A. ; Boiano, A. ; Vardaci, E. ; Zaghi, A. ; Brondi, A.
Author_Institution :
Ist. Nazionale di Fisica Nucl., Napoli, Italy
fDate :
6/1/1998 12:00:00 AM
Abstract :
FAIR (FAst Intercrate Readout) is a synchronous ECL bus system dedicated to readout. It is based on a new trigger and readout hardware level protocol and an on a new control system that “learns” how to setup and control modules. The hardware protocol along with the data structure allow both readout and event building at the same time at the rate of 22 ns/longword (1.44 Gbit/s) without the need of CPUs. It performs trigger management and full pipelining by using a multilevel FIFO structure. FAIR provides for a multi-crate front-end environment and uses an embedded serial network to accomplish front-end control and setup. The data transfer measured performances and the control system are presented in some detail
Keywords :
digital readout; emitter-coupled logic; nuclear electronics; peripheral interfaces; protocols; system buses; trigger circuits; 1.44 Gbit/s; FAIR; control system; data transfer; embedded serial network; event building; hardware protocol; multi-crate front-end environment; multilevel FIFO structure; pipelining; readout bus; synchronous ECL bus system; trigger; CAMAC; Control systems; Data structures; Detectors; Energy management; Fastbus; Hardware; Pipeline processing; Protocols; Scalability;
Journal_Title :
Nuclear Science, IEEE Transactions on
