• DocumentCode
    1390816
  • Title

    A Novel Array-Based Test Methodology for Local Process Variation Monitoring

  • Author

    Luo, Tseng-Chin ; Chao, Mango C -T ; Wu, Michael S -Y ; Li, Kuo-Tsai ; Hsia, Chin C. ; Tseng, Huan-Chi ; Fisher, Philip A. ; Huang, Chuen-Uan ; Chang, Yuan-Yao ; Pan, Samuel C. ; Young, Konrad K -L

  • Author_Institution
    Taiwan Semicond. Manuf. Corp., Hsinchu, Taiwan
  • Volume
    24
  • Issue
    2
  • fYear
    2011
  • fDate
    5/1/2011 12:00:00 AM
  • Firstpage
    280
  • Lastpage
    293
  • Abstract
    As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for integrated circuit manufacturing. To monitor local process variation, a large number of devices-under-test (DUTs) in close proximity must be measured. In this paper, we present a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by application of the test techniques proposed in this paper: hardware IR compensation, voltage bias elevation, and leakage-current cancelation. Furthermore, the DUT layout need not be modified for the proposed test structure. Thus, the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.
  • Keywords
    integrated circuit testing; leakage currents; process monitoring; array-based test methodology; array-based test structure; devices-under-test; hardware IR compensation; integrated circuit manufacturing; leakage-current cancelation; local process variation monitoring; voltage bias elevation; Arrays; Current measurement; Layout; Logic gates; Resistance; Transistors; Voltage measurement; Automatic test equipment; measurement techniques; mismatch; process variation; test structure design; test structures; transistor array;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2010.2095891
  • Filename
    5648466