Title :
A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS
Author :
Qazi, Masood ; Stawiasz, Kevin ; Chang, Leland ; Chandrakasan, Anantha P.
Author_Institution :
Microsyst. Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2V down to 0.57V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the contents of the memory.
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; intelligent sensors; low-power electronics; silicon-on-insulator; AC-coupled sense amplifier; SOI CMOS; SRAM macro; Si; area efficient data path; data retention voltage sensor; embedded data-retention-voltage sensor; low voltage operation; mismatch-limited minimum standby voltage; regenerative global bitline scheme; size 45 nm; timing variation; voltage 1.2 V to 0.57 V; voltage scalable operation; Arrays; CMOS integrated circuits; Couplings; Delay; Random access memory; Sensors; CMOS memory circuits; Cache memories; SRAM chips; leakage currents; low-power electronics; offset compensation; process variation; random-access storage; sense-amplifier; voltage scaling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2085970
