• DocumentCode
    1391156
  • Title

    Application of port-access-rejection probability theory for integrated N-port memory architecture optimisation

  • Author

    Mattausch, H.J. ; Yamada, K.

  • Author_Institution
    Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
  • Volume
    34
  • Issue
    9
  • fYear
    1998
  • fDate
    4/30/1998 12:00:00 AM
  • Firstpage
    861
  • Lastpage
    862
  • Abstract
    Area-efficient architectures for integrated N-port memories employ blocks of one port memory cells and dynamic port-to-block connections. The authors determine the block number M necessary to achieve a target port-access-rejection probability for a given port number N and best-case/worst-case conflict-resolve algorithms, by applying stochastic probability theory
  • Keywords
    cellular arrays; circuit optimisation; memory architecture; multiport networks; probability; stochastic processes; area-efficient architectures; conflict-resolve algorithms; dynamic port-to-block connections; integrated N-port memory architecture; memory architecture optimisation; one port memory cells; port-access-rejection probability theory; stochastic probability theory;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980649
  • Filename
    682812
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1391156