Title :
Application of port-access-rejection probability theory for integrated N-port memory architecture optimisation
Author :
Mattausch, H.J. ; Yamada, K.
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
fDate :
4/30/1998 12:00:00 AM
Abstract :
Area-efficient architectures for integrated N-port memories employ blocks of one port memory cells and dynamic port-to-block connections. The authors determine the block number M necessary to achieve a target port-access-rejection probability for a given port number N and best-case/worst-case conflict-resolve algorithms, by applying stochastic probability theory
Keywords :
cellular arrays; circuit optimisation; memory architecture; multiport networks; probability; stochastic processes; area-efficient architectures; conflict-resolve algorithms; dynamic port-to-block connections; integrated N-port memory architecture; memory architecture optimisation; one port memory cells; port-access-rejection probability theory; stochastic probability theory;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980649
