Title :
Latency minimisation by system clock optimisation
Author :
Park, Sanghun ; Choi, Kuyounhg
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
fDate :
4/30/1998 12:00:00 AM
Abstract :
Performance of a system clock design depends on the operating clock period and cycle count, which is the same as the number of control steps for a design without loops. A method is proposed which maximises performance by adjusting the clock period and cycle count. Experimental results show that this method reduces the latency by 29.4% on average, compared to the conventional high-level synthesis method
Keywords :
circuit optimisation; clocks; high level synthesis; minimisation of switching nets; clock period; cycle count; high-level synthesis method; latency minimisation; operating clock period; system clock optimisation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980664
