Title :
Via assignment in single-row routing
Author :
Bhasker, Jayaram ; Sahni, Sartaj
Author_Institution :
AT&T Bell Labs., Middletown, PA, USA
fDate :
1/1/1989 12:00:00 AM
Abstract :
Examines the via assignment problem that arises when the single-row routing approach to the interconnection problem is used. Some new complexity results and two new heuristics are obtained. Experimental results establish the superiority of the new heuristics over earlier ones
Keywords :
circuit layout CAD; computational complexity; printed circuit design; complexity results; heuristics; interconnection; multilayer PCB; single-row routing; via assignment; Computer science; Integrated circuit interconnections; Minimization; Nonhomogeneous media; Pins; Polynomials; Printed circuits; Routing;
Journal_Title :
Computers, IEEE Transactions on
