DocumentCode
1391493
Title
MOS Devices With High-κ (ZrO 
) 
(La <i>x</i>(La<sub>2</sub>O<sub>3</sub>)<sub>1-x</sub> alloy formed by depositing a ZrO<sub>2</sub>/La<sub>2</sub>O<sub>3</sub>/ZrO<sub>2</sub> laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices. The (ZrO<sub>2</sub>)<sub>x</sub>(La<sub>2</sub>O<sub>3</sub>)<sub>1-x</sub> alloy is found to have a high permittivity κ of 26.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. By integrating the (ZrO<sub>2</sub>)<i>x</i>(La <sub>2</sub>O<sub>3</sub>)<sub>1-x</sub> alloy with an SiON interfacial layer as the gate stack, it displays good frequency dispersion in capacitance-voltage (<i>C</i> -<i>V</i>) characteristics and low interfacial trap density of 1.52 × 10<sup>11</sup> cm<sup>-2</sup> eV<sup>-1</sup>. In addition, the current conduction mechanism of the gate stack is observed to be Fowler-Nordheim tunneling and the leakage current of 3.6 × 10<sup>-6</sup> A/cm<sup>2</sup> at the gate voltage of -1 V for equivalent oxide thickness of 1.1 nm can be achieved, which is superior to other high-κ dielectrics. Furthermore, satisfactory reliability is verified by bias temperature instability measurement. Most importantly, this gate stack not only exhibits a promising perspective for advanced CMOS technology but introduces a more reliable process to form an alloy-based high-κ gate dielectric.</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>CMOS integrated circuits; MIS devices; amorphous magnetic materials; annealing; high-k dielectric thin films; laminates; lanthanum compounds; leakage currents; permittivity; reliability; zirconium compounds; (ZrO<sub>2</sub>)<sub>x</sub>(La<sub>2</sub>O<sub>3</sub>)<sub>1-x</sub>; CMOS technology; Fowler-Nordheim tunneling; MOS devices; SiON interfacial layer; ZrO<sub>2</sub>-La<sub>2</sub>O<sub>3</sub>-ZrO<sub>2</sub> laminate; amorphous (ZrO<sub>2</sub>)<sub>x</sub>(La <sub>2</sub>O<sub>3</sub>)<sub>1-x</sub> alloy; annealing; bias temperature instability measurement; capacitance-voltage characteristics; current conduction mechanism; frequency dispersion; gate dielectric; gate stack; high-κ (ZrO<sub>2</sub>)<sub>x</sub>(La <sub>2</sub>O<sub>3</sub>)<sub>1</sub><sub>-</sub><sub>x</sub> alloy; interfacial trap density; leakage current; metal-oxide-semiconductor devices; permittivity; reliability; size 1.1 nm; Annealing; Dielectrics; Frequency measurement; Laminates; Logic gates; Metals; Silicon; (ZrO<formula formulatype=)
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fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2011.2178612
Filename
6096419
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