Title :
Power estimation method for highly correlated input sequences under realistic delay model
Author :
Kim, Hansoo ; Choi, Hoon ; Hwang, Seung Ho
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
5/14/1998 12:00:00 AM
Abstract :
A new power estimation method is presented which considers spatio-temporal correlations among the primary inputs as well as the glitch effect under a realistic delay model. To deal with the glitch effect, the symbolic simulation technique is employed, and to take the correlations among the primary inputs into account, the authors employ a new technique which transforms correlation information into a logic structure, called `pre-logic´. Experimental results show that the estimation error of the proposed method is ~4% under a realistic delay model with highly correlated input streams
Keywords :
binary sequences; delays; logic circuits; glitch effect; logic circuits; power estimation method; prelogic structure; realistic delay model; spatio-temporal correlations; symbolic simulation technique;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980688