Title :
High-gain emitter inversion layer PNP vertical bipolar transistor in compensated CMOS technology
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
fDate :
5/14/1998 12:00:00 AM
Abstract :
To improve the value of β of a pnp-merged vertical bipolar transistor (VET) in `pseudo-BiCMOS´ technology, a novel VBT design with an inversion layer-extended emitter is proposed. A high emitter injection efficiency of the forward-biased inversion layer is demonstrated in a pnp VET fabricated in 1 μm compensated CMOS technology
Keywords :
BiCMOS integrated circuits; bipolar transistors; integrated circuit design; inversion layers; PNP vertical bipolar transistor; VBT; compensated CMOS technology; emitter injection efficiency; emitter inversion layer; forward-biased inversion layer; pseudo-BiCMOS technology;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980732
