Title :
Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA
Author :
Grossmann, P.J. ; Leeser, Miriam E. ; Onabajo, Marvin
Author_Institution :
MIT Lincoln Lab., Lexington, MA, USA
Abstract :
Field-programmable gate arrays (FPGAs) are an attractive option for low-power systems requiring flexible computing resources. However, the lowest power systems have yet to adopt FPGAs. Subthreshold circuit operation offers the opportunity to operate FPGAs at their minimum energy point. This paper presents data measured from an FPGA test chip fabricated in a 0.18-μm SOI process. It is shown that the test chip can function at supply voltages as low as 0.26 V without an extra supply for write assists by using latches for configuration bit storage instead of static random access memory. Investigation of the minimum energy point of the FPGA for a high-activity test pattern shows that the minimum energy point of the FPGA can be well below the threshold voltage of the transistors.
Keywords :
field programmable gate arrays; flip-flops; low-power electronics; SOI process; configuration bit storage; field-programmable gate arrays; flexible computing resources; high-activity test pattern; latch-based subthreshold FPGA; low-power systems; minimum energy point; size 0.18 mum; subthreshold circuit operation; threshold voltage; write assists; Field programmable gate arrays; Logic gates; Low power electronics; Low voltage; Random access memory; Semiconductor device measurement; Transistors; Field-programmable gate array (FPGA); low-power design; minimum energy operation; power-delay product; subthreshold FPGA; variation-aware design;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2012.2231035
