Novel cell architecture for bit level systolic arrays multiplication

A novel cell architecture for bit level systolic array multiplication is presented. It is used for the design of a serial-parallel and an iterative pipelined multiplier. The new architecture is a result of combining, in a novel way, the operation of a two gated full-adder cell used in conventional multipliers. The new cell circumvents the insertion of zeros in structures with contraflow data streams. As a result, the array is used with 100% efficiency, and the throughput rate is doubled in comparison to most systolic arrays using the contraflowing approach. This is achieved without any increase in hardware, nor the use of a special clock circuitry. Performance analysis of the new multipliers and existing ones has shown the superiority of the new architecture.