• DocumentCode
    1392967
  • Title

    A new heuristic for rectilinear Steiner trees

  • Author

    Mandoiu, Ion I. ; Vazirani, Vijay V. ; Ganley, Joseph L.

  • Author_Institution
    Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
  • Volume
    19
  • Issue
    10
  • fYear
    2000
  • fDate
    10/1/2000 12:00:00 AM
  • Firstpage
    1129
  • Lastpage
    1139
  • Abstract
    The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1-Steiner (BI1S) heuristic of Kahng and Robins. In a recent development, exact RST algorithms have witnessed spectacular progress: The new release of the GeoSteiner code of Warme et al. has average running time comparable to that of the fastest available BI1S implementation, due to Robins. We are, thus, faced with the paradoxical situation that an exact algorithm for an NP-hard problem is competitive in speed with a state of-the-art heuristic for the problem. The main contribution of this paper is a new RST heuristic, which has at its core a recent 3/2 approximation algorithm of Rajagopalan and Vazirani for the metric Steiner tree problem on quasi-bipartite graphs-these are graphs that do not contain edges connecting pairs of Steiner vertices. The RV algorithm is built around the linear programming relaxation of a sophisticated integer program formulation, called the bidirected cut relaxation. Our heuristic achieves a good running time by combining an efficient implementation of the RV algorithm with simple, but powerful geometric reductions. Experiments conducted on both random and real very large scale integrated instances show that the new RST heuristic runs significantly faster than Robins´ implementation of BI1S and than the GeoSteiner code. Moreover, the new heuristic typically gives higher-quality solutions than BI1S
  • Keywords
    VLSI; circuit layout CAD; circuit optimisation; computational complexity; integer programming; integrated circuit interconnections; integrated circuit layout; linear programming; network routing; trees (mathematics); 3/2 approximation algorithm; NP-hard; RST heuristic; bidirected cut relaxation; electronic design automation; geometric reductions; heuristic; integer program formulation; linear programming relaxation; quasi-bipartite graphs; rectilinear Steiner trees; running time; solution quality; very large scale integrated instances; Algorithm design and analysis; Approximation algorithms; Electronic design automation and methodology; Heuristic algorithms; Integrated circuit interconnections; Joining processes; Linear programming; NP-hard problem; Routing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.875292
  • Filename
    875292