Title :
Automated synthesis of phase shifters for built-in self-test applications
Author :
Rajski, Janusz ; Tamarapalli, Nagesh ; Tyszer, Jerzy
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
fDate :
10/1/2000 12:00:00 AM
Abstract :
This paper presents novel systematic design techniques for the automated register transfer level synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by pseudorandom test pattern generators driving parallel scan chains. Using a concept of linear feedback shift register (LFSR) duality this paper relates the logical states of LFSRs and circuits spacing their inputs to each of the output channels. Consequently, the method generates a phase-shifter network satisfying criteria of channel separation and circuit complexity by taking advantage of simple logic simulation of the LFSRs. It is shown that it is possible to synthesize in a time-efficient manner very large and fast phase shifters for built-in self-test applications with guaranteed minimum phaseshifts between scan chains, and very low delay and area of virtually one two-way XOR gate/channel
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; delays; high level synthesis; logic simulation; phase shifters; shift registers; automated synthesis; built-in self-test applications; channel separation; circuit complexity; delay; linear feedback shift register duality; logic simulation; output channels; parallel scan chains; phase shifters; pseudorandom test pattern generators; register transfer level synthesis; scan chains; structural dependencies; systematic design techniques; two-way XOR gate/channel; Built-in self-test; Circuit simulation; Circuit synthesis; Complexity theory; Feedback circuits; Linear feedback shift registers; Logic circuits; Network synthesis; Phase shifters; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
