Title :
Implicit enumeration of strongly connected components and an application to formal verification
Author :
Xie, Aiguo ; Beerel, Peter A.
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
fDate :
10/1/2000 12:00:00 AM
Abstract :
This paper first presents a binary decision diagram-based implicit algorithm to compute all maximal strongly connected components (SCCs) of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experimental results suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacency-matrix of the graphs. This paper then applies this SCC algorithm to solve the bad cycle detection problem encountered in formal verification. Experimental results show that our new bad cycle detection algorithm is typically significantly faster than the state-of-the-art, sometimes by more than a factor of ten
Keywords :
binary decision diagrams; circuit CAD; directed graphs; formal verification; integrated circuit design; logic CAD; SCC algorithm; bad cycle detection problem; binary decision diagram; directed graphs; formal verification; implicit enumeration; maximal strongly connected components; strongly connected components; Application software; Automata; Boolean functions; Data structures; Design automation; Detection algorithms; Formal verification; Iterative algorithms; Reachability analysis; State-space methods;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on