Switching Loss Analysis Considering Parasitic Loop Inductance With Current Source Drivers for Buck Converters

In this letter, the switching loop inductance was investigated on the current-source drivers (CSDs). The analytical model was developed to predict the switching losses. It is noted that although the CSDs can greatly reduce the switching transition time and switching loss, the switching loop inductance still causes the current holding effect on the CSDs. This results in high turn-off loss for the control MOSFET in a buck converter. An improved layout was proposed to achieve minimum switching loop inductance. The experimental results verified the significant switching loss reduction owing to the proposed layout of a 1-MHz buck converter with 12-V input, and 1.3-V and 30-A output.