Architectural partitioning for system level synthesis of integrated circuits

Author

Lagnese, Elizabeth Dirkes ; Thomas, Donald E.

Author_Institution

Dept. of Eletr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

10

Issue

7

fYear

1991

fDate

7/1/1991 12:00:00 AM

Firstpage

847

Lastpage

860

Abstract

APARTY is an architectural partitioning tool that uses a novel multistage clustering algorithm to extract the high level structure of an IC design by concentrating on area and interconnect considerations. Performance is addressed implicitly. APARTY works within the framework of the system architect´s workbench and can pass system-level structural information along to register-transfer level (RTL) tools to guide the completion of a data-path design. The multistage clustering algorithm and how it is used by APARTY to choose partitions are described. The system architect´s workbench and how architectural partitioning can be used to guide synthesis are also described. Results of using APARTY in the design process show improved register-transfer designs. In particular, the number of global routing wires is generally reduced by over 50% by following the partitioning scheme suggested by APARTY

Keywords

circuit CAD; circuit layout CAD; integrated circuit technology; APARTY; CAD; IC design; IC layout; RTL tools; architectural partitioning tool; data-path design; global routing wires; high level structure; integrated circuits; multistage clustering algorithm; register-transfer level; system level synthesis; system-level structural information; Feeds; Global communication; Hardware; Integrated circuit interconnections; Integrated circuit synthesis; Parallel processing; Process design; Routing; System-level design; Wires;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.87596

Filename

87596