DocumentCode
1393861
Title
A new methodology for the design centering of IC fabrication processes
Author
Low, K.K. ; Director, Stephen W.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Volume
10
Issue
7
fYear
1991
fDate
7/1/1991 12:00:00 AM
Firstpage
895
Lastpage
903
Abstract
The authors describe a practical methodology that can be applied to optimize the process yield of IC fabrication lines. The yield maximization problem is first reformulated into a deterministic design centering problem. Macromodeling and problem decomposition are then applied to solve the design centering problem efficiently. The effectiveness of this methodology is illustrate through a simulation example involving a CMOS process adopted from an industrial line
Keywords
integrated circuit manufacture; integrated circuit technology; optimisation; CMOS process; IC fabrication processes; design centering; macromodelling; problem decomposition; process yield; yield maximization; CMOS process; Circuits; Design methodology; Fabrication; Fluctuations; Optimization methods; Oxidation; Process control; Process design; Threshold voltage;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.87599
Filename
87599
Link To Document