DocumentCode :
1393883
Title :
Ratio cut partitioning for hierarchical designs
Author :
Wei, Yen-Chuen ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
Volume :
10
Issue :
7
fYear :
1991
fDate :
7/1/1991 12:00:00 AM
Firstpage :
911
Lastpage :
921
Abstract :
Circuit partitioning for hierarchical VLSI design is addressed. A partitioning approach called ratio cut is proposed. It is demonstrated that the ratio cut algorithm can locate the clustering structures in the circuit. Finding the optimal ratio cut is NP-complete. However, in certain cases the ratio cut can be solved by linear programming techniques via the multicommodity flow formulation. Also proposed is a fast heuristic algorithm running in linear time with respect to the number of pins in the circuit. Experiments show good results in all tested cases
Keywords :
VLSI; circuit CAD; integrated circuit technology; linear programming; CAD; NP-complete; clustering structures; fast heuristic algorithm; hierarchical VLSI design; linear programming; multicommodity flow formulation; partitioning; ratio cut algorithm; Circuit optimization; Circuit testing; Clustering algorithms; Costs; Linear programming; Matrix decomposition; Partitioning algorithms; Pins; Silicon; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.87601
Filename :
87601
Link To Document :
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