• DocumentCode
    1393888
  • Title

    Fast batch incremental netlist compilation hierarchical schematics

  • Author

    Jones, Larry G.

  • Author_Institution
    Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
  • Volume
    10
  • Issue
    7
  • fYear
    1991
  • fDate
    7/1/1991 12:00:00 AM
  • Firstpage
    922
  • Lastpage
    931
  • Abstract
    Fast batch and incremental algorithms for creating and updating the netlist underlying a hierarchical schematic design are presented. The algorithms can be used either for maintaining the netlist as a data structure for further online processing or as a file for use with other offline design tools that are downstream from the compilation process. The batch algorithm uses a preorder traversal of the design hierarchy to derive the netlist. The incremental algorithm trims this traversal to only those paths leading to changes in the netlist. For most user modifications the netlist can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no perceivable delay to the user
  • Keywords
    circuit CAD; data structures; batch algorithm; data structure; hierarchical schematics; incremental algorithms; incremental netlist compilation; netlist updating; preorder traversal; schematic design; Algorithm design and analysis; Circuit simulation; Data structures; Delay effects; Design methodology; Fasteners; Helium; Logic design; Pins; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.87602
  • Filename
    87602