DocumentCode :
1393892
Title :
Easily testable gate-level and DCVS multipliers
Author :
Takach, Andres R. ; Jha, Niraj K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Volume :
10
Issue :
7
fYear :
1991
fDate :
7/1/1991 12:00:00 AM
Firstpage :
932
Lastpage :
942
Abstract :
Some C-testable designs of a carry-save parallel multiplier are presented. Results are given for both the gate-level implementation and the differential cascode voltage switch (DCVS) implementation. DCVS circuits are dynamic CMOS circuits which have the advantage of being protected against test set invalidation due to circuit delays. In the first gate-level design, it is assumed that the full-adders have any arbitrary, irredundant logic implementation. Such a design is C-testable with only nine test vectors, which detect all single stuck-at-faults. For a specific logic implementation of the full-adders, another design is shown to be C-testable with only six test vectors. The DCVS design is also C-testable with only six test vectors, which detect all detectable stuck-at, and stuck-open faults in the circuit. Both the hardware and delay overhead for all C-testable designs are very small. For three C-testable designs of the 32 by 32 multiplier, the hardware overhead is 2.7% or less and the delay overhead is 2.4% or less
Keywords :
carry logic; digital arithmetic; logic design; logic testing; multiplying circuits; C-testable designs; DCVS multipliers; carry-save parallel multiplier; differential cascode voltage switch; dynamic CMOS circuits; full-adders; gate-level implementation; testable gate-level; Circuit testing; Delay; Electrical fault detection; Fault detection; Hardware; Logic design; Logic testing; Protection; Switches; Voltage;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.87603
Filename :
87603
Link To Document :
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