Asymmetric large size multipliers with optimised FPGA resource utilisation

In this study, asymmetric non-pipelined large size unsigned and signed multipliers are implemented using symmetric and asymmetric embedded multipliers, look-up tables and dedicated adders in field programmable gate arrays (FPGAs). Decompositions of the operands are performed for the efficient use of the embedded blocks. Partial products are organised in various configurations, and the additions of the products are realised in an optimised manner. The additions used in the implementation of the multiplication include compressor-based, Delay-Table and Ternary-adder-based approaches. These approaches have led to the minimisation of the total critical path delay with reduced utilisation of FPGA resources. The asymmetric multipliers were implemented in Xilinx FPGAs using 18×18-bit and 25×18-bit embedded signed multipliers. Implementation results demonstrate an improvement of up to 32× in delay and up to 37× in the number of embedded blocks compared with the performance of designs generated by commercial synthesis tools.