A parasitics extraction and network reduction algorithm for analog VLSI

Author

Pong, Teng-Sin ; Brooke, Martin A.

Author_Institution

Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

10

Issue

2

fYear

1991

fDate

2/1/1991 12:00:00 AM

Firstpage

145

Lastpage

149

Abstract

A transmission line model for the extraction of circuit parasitics in integrated circuits is presented. This model is shown to give a better account of the DC and aC characteristics of interconnects than models incorporating exclusively the R or C components. A network-reduction technique that is used to simplify the extracted RC network at user-specified accuracies to manageable complexities, especially for large VLSI circuits, is also discussed. The model and circuit reduction algorithms are applied to practical sample circuits and results of simulations illustrating the reduction in circuit complexity and the degree of modeling accuracy by these methods are given

Keywords

VLSI; equivalent circuits; linear integrated circuits; semiconductor device models; transmission line theory; DC characteristics; aC characteristics; analog VLSI; extracted RC network; integrated circuits; interconnects; large VLSI circuits; network reduction algorithm; parasitics extraction; simulations; transmission line model; Analog circuits; Analog integrated circuits; Circuit simulation; Complexity theory; Distributed parameter circuits; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit technology; Transmission line theory; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.68401

Filename

68401