DocumentCode :
1393974
Title :
Scheduling blocks of hierarchical compiled simulation of combinational circuits
Author :
Maurer, Peter M.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Volume :
10
Issue :
2
fYear :
1991
fDate :
2/1/1991 12:00:00 AM
Firstpage :
184
Lastpage :
192
Abstract :
Several algorithms for scheduling high-level functional blocks that assume the blocks may not be physically divided and that pseudocycles may be present due to the grouping of elements within blocks are presented. These algorithms rely on dependency information derived from the block-definitions to create a logical (rather than physical) partitioning of the circuit. The partitioned network is scheduled by an algorithm that is based on levelized scheduling with various heuristics added. The choice of the algorithm is based on the randomness of the partitioning technique. For highly random partitioning, PCSF performs best, while for partitioning that conforms closely to the signal flow of the circuit, FIQ performs best. For circuits in between, MEO is shown to perform best. These techniques represent an improvement over the technique of simulating blocks in random order, since no block will be scheduled unless there is a potential for performing useful work by simulating the block. The problem of finding the minimal schedule is shown to be NP-complete, hence, a heuristic approach to the problem is justified. A technique for computing the dependencies of a block is also presented
Keywords :
circuit analysis computing; combinatorial circuits; computational complexity; logic CAD; scheduling; FIQ; MEO; NP complete problem; PCSF; combinational circuits; hierarchical compiled simulation; high-level functional blocks; logic circuits; minimal schedule; partitioned network; partitioning technique; scheduling; Adders; Algorithms; Circuit simulation; Combinational circuits; Computational modeling; Computer science; Discrete event simulation; Processor scheduling; Sequential circuits;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.68405
Filename :
68405
Link To Document :
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