A Markov chain-based yield formula for VLSI fault-tolerant chips

Author

Ciciani, Bruno ; Iazeolla, Giuseppe

Author_Institution

Dept. of Electron. Eng., Rome Univ., Italy

Volume

10

Issue

2

fYear

1991

fDate

2/1/1991 12:00:00 AM

Firstpage

252

Lastpage

259

Abstract

A yield calculation method for the yield formula of fault-tolerant VLSI chips that improves existing methods and combines generalities, ease of computation, and predictability in approximation levels is presented. The method is concerned with the evaluation of the probability that a chip is acceptable given n defects. This is accomplished by introducing a Markov chain model in which each state represents an operating chip configuration, and the state transitions take place in the presence of manufacturing defects. Results from the comparison of this method to a method for memory chip yield evaluation, a method for the M-out-of-N yield problem evaluation, and a method for the square grid chip yield evaluation are presented

Keywords

Markov processes; VLSI; circuit reliability; probability; statistical analysis; Markov chain model; VLSI fault-tolerant chips; probability; yield calculation method; yield formula; Circuit faults; Fault tolerance; Logic circuits; Logic devices; Probability; Redundancy; State-space methods; Statistics; Very large scale integration; Virtual manufacturing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.68412

Filename

68412