DocumentCode
1394055
Title
Estimating the minimum of partitioning and floorplanning problems
Author
Sastry, Sarma ; Pi, Jen-I
Author_Institution
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Volume
10
Issue
2
fYear
1991
fDate
2/1/1991 12:00:00 AM
Firstpage
273
Lastpage
282
Abstract
The statistical properties of two combinatorial optimization problems that arise in the physical design of circuits, circuit partitioning, and floorplanning, are discussed. For the partitioning problem, the solutions generated by the Kernighan-Lin (1970) procedure and those generated by a random search are examined. It is shown that in both cases, the Type 3 (Weibull) extreme value distribution provides an excellent model for the distribution of local minima generated. The location parameter of the Weibull provides an estimate of the minimum cost. Various techniques that were used to estimate the parameters of the Weibull are discussed, and ample empirical evidence to support the hypothesis is provided. For the floorplanning problem, a number of test problems whose optimal value are known are constructed. By using a representation of slicing floorplans developed by D.F. Wong and C.L. Liu (1986), the solution space is randomly sampled and a number of local minima are generated. As with the partitioning problem, it is found that the Weibull distribution provides an excellent model for estimating the minimum cost
Keywords
circuit layout; combinatorial mathematics; optimisation; parameter estimation; search problems; statistical analysis; Type 3; Weibull distribution; circuit partitioning; combinatorial optimization problems; extreme value distribution; floorplanning; local minima generation; minimum cost estimation; model; random search; statistical properties; Chip scale packaging; Circuits; Costs; Design optimization; Multidimensional systems; Optimization methods; Routing; Semiconductor device measurement; Statistical analysis; Stochastic processes;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.68416
Filename
68416
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