• DocumentCode
    1394140
  • Title

    CMOS dynamic ternary circuit with full logic swing and zero-static power consumption

  • Author

    Toto, F. ; Saletti, R.

  • Author_Institution
    Dipt. di Ingegneria dell´´Inf. Elettronica Inf. Telecommun., Pisa Univ., Italy
  • Volume
    34
  • Issue
    11
  • fYear
    1998
  • fDate
    5/28/1998 12:00:00 AM
  • Firstpage
    1083
  • Lastpage
    1084
  • Abstract
    A new dynamic circuit scheme to realise ternary logic is presented. The main properties are the use of the standard CMOS process without any modification of the thresholds, the minimum possible number of external voltage levels (three), the highest possible logic swing and noise margins and the absence of static power consumption
  • Keywords
    CMOS logic circuits; logic design; logic gates; multivalued logic circuits; ternary logic; CMOS dynamic ternary circuit; full logic swing; noise margins; standard CMOS process; ternary inverter; ternary logic; zero-static power consumption;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980754
  • Filename
    684326
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1394140