Fault Modeling and Worst-Case Test Vectors for Leakage Current Failures Induced by Total Dose in ASICs

We developed a cell-level fault model for leakage current failure of standard-cell ASIC devices exposed to total ionizing dose. This fault model is valid for CMOS process technologies that exhibit field-oxide leakage current under total dose. The fault model was represented using hardware descriptive languages which consequently allowed for cell-level simulation of ASIC devices under total dose using functional simulation tools normally used during the design flow of ASIC devices. However, the identification of worst-case test vectors using those tools using automatic test pattern generation (ATPG) tools targeting the fault model developed. This can lead to prohibitively long search time for WCTV in large ASIC devices. We developed an innovative search method based on genetic algorithms (GA) which made possible the identification of WCTV for large ASIC devices in very short time. Finally, we experimentally validated the significance of WCTV in total dose testing of ASIC devices.