Title :
A 133 MHz Radiation-Hardened Delay-Locked Loop
Author :
Sengupta, Rajat ; Vermeire, Bert ; Clark, Lawrence T. ; Bakkaloglu, Bertan
Author_Institution :
Dept. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA
Abstract :
A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 μ m fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented.
Keywords :
circuit layout; delay lock loops; error correction; memory architecture; network synthesis; radiation hardening (electronics); DDR memory; delay-locked loop architecture; error-correction logic; fabrication process; frequency 133 MHz; hardened digital integrator; layout technique; quadrature phase clock generation; radiation hardening; single-event transients; Charge pumps; Phase locked loops; Single event transient; Tracking loops; Charge pump; delay-locked loop (DLL); jitter phase-locked loop (PLL); single-event transients (SETs);
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2010.2086485
