DocumentCode :
1394669
Title :
Design, analysis, and evaluation of concurrent checking sorting networks
Author :
Kantawala, K.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Volume :
5
Issue :
3
fYear :
1997
Firstpage :
338
Lastpage :
343
Abstract :
In this brief, we propose two new concurrent error-detection (CED) schemes for a class of sorting networks, e.g., odd-even transposition, bitonic, and perfect shuffle sorting networks. A probabilistic method is developed to analyze the fault coverage, and the hardware overhead is evaluated. We first propose a CED scheme by which all errors caused by single faults in a concurrent checking sorting network can be detected. This scheme is the first one available to use significantly less hardware overhead than duplication without compromising throughput. From this scheme, we develop another fault detection scheme which sharply reduces the hardware overhead (using an additional 10%/spl sim/30% hardware) but still achieves virtually 1001 fault coverage.
Keywords :
VLSI; error detection; fault diagnosis; parallel processing; sorting; array processors; bitonic networks; concurrent checking sorting networks; concurrent error-detection; fault coverage; fault detection scheme; hardware overhead; odd-even transposition; perfect shuffle sorting networks; probabilistic method; throughput; totally self checking; Circuit faults; Data processing; Electrical fault detection; Fault detection; Fault tolerance; Hardware; Signal processing; Sorting; Throughput; Very large scale integration;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.609877
Filename :
609877
Link To Document :
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