LDD MOSFETs using disposable sidewall spacer technology

Author

Pfiester, James R.

Author_Institution

Motorola, Austin, TX, USA

Volume

9

Issue

4

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

189

Lastpage

192

Abstract

A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n/sup -/ and n/sup +/ or p/sup -/ and p/sup +/ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K*4 SRAM circuit using a conventional 1.5- mu CMOS technology.<>

Keywords

CMOS integrated circuits; field effect integrated circuits; insulated gate field effect transistors; integrated circuit technology; 1.5 micron; CMOS process; CMOS technology; IC fabrication; LDD MOSFETs; NMOS; PMOS; SRAM circuit; Si; disposable sidewall spacer technology; fabrication; lightly doped drain; low-temperature oxide; masking; oxidized polysilicon gate; polycrystalline semiconductor; polysilicon buffer layer; source/drain implants; wet HF strip; Buffer layers; CMOS process; CMOS technology; Hafnium; Implants; MOS devices; MOSFETs; Space technology; Strips; Wet etching;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.685

Filename

685