A methodology to study lateral parasitic transistors in CMOS technologies

This work concerns the development of a methodology specially devoted to lateral parasitic transistors that limit the total dose hardness of CMOS technologies. This methodology is based on i) the irradiation of standard NMOS transistors followed by ii) isochronal annealing measurements to determine energetic spectra of the field oxide trapped charge. Post irradiation effects have been evaluated through additional isothermal annealing experiments at 75°C which are consistent with isochronal results. We propose a test procedure which allows to determine physical parameters helpful to improve comparison and qualification Of CMOS commercial technologies