• DocumentCode
    1394791
  • Title

    Demonstration of a Differential Layout Solution for Improved ASET Tolerance in CMOS A/MS Circuits

  • Author

    Armstrong, S.E. ; Olson, B.D. ; Holman, W.T. ; Warner, J. ; McMorrow, D. ; Massengill, L.W.

  • Author_Institution
    NAVSEA Crane, Crane, IN, USA
  • Volume
    57
  • Issue
    6
  • fYear
    2010
  • Firstpage
    3615
  • Lastpage
    3619
  • Abstract
    Layout techniques that exploit charge-sharing phenomena for analog single-event transient (ASET) mitigation in fully-differential analog/mixed-signal (A/MS) designs are experimentally explored in a 65 nm CMOS process. Benefits of the proposed RHBD layout techniques are illustrated through circuit simulations. Preliminary RHBD layout guidelines are discussed.
  • Keywords
    CMOS integrated circuits; circuit simulation; integrated circuit layout; radiation effects; 65 nm CMOS process; ASET tolerance; CMOS A/MS Circuits; RHBD layout; analog single-event transient mitigation; charge-sharing phenomena; circuit simulation; differential layout solution; fully-differential analog/mixed-signal designs; CMOS technology; Circuit simulation; Radiation hardening; Single event transient; Charge sharing; radiation hardened by design; single event effects; single event transients;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2010.2080320
  • Filename
    5658059
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1394791