• DocumentCode
    1394798
  • Title

    Parametric Variability Affecting 45 nm SOI SRAM Single Event Upset Cross-Sections

  • Author

    Loveless, Thomas Daniel ; Alles, Michael L. ; Ball, Dennis R. ; Warren, Kevin M. ; Massengill, Lloyd W.

  • Author_Institution
    Inst. of Space & Defense Electron., Vanderbilt Univ., Nashville, TN, USA
  • Volume
    57
  • Issue
    6
  • fYear
    2010
  • Firstpage
    3228
  • Lastpage
    3233
  • Abstract
    SEU simulation analyses of a commercial 45 nm CMOS SOI SRAM cell compared to test data highlight the need to better understand and account for variation in inter-cell hardness, and uncertainty in energy deposition in small sensitive volumes. Simulations indicate that operating voltage and body resistance have the largest impact on simulated cell hardness.
  • Keywords
    CMOS memory circuits; SRAM chips; nuclear electronics; silicon-on-insulator; CMOS SOI SRAM; SEU simulation analysis; intercell hardness; parametric variability; single event upset cross section; CMOS technology; SRAM chips; Silicon on insulator technology; Simulation; Single event upset; CMOS; SRAM; silicon-on-insulator (SOI); simulation; single event upset (SEU);
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2010.2081688
  • Filename
    5658060
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1394798